===============================
Hardware Implementation Results
===============================

The Frontend Part was converted to VHDL and synthesized using Vivado 2014.4. The 
stategy which used for the implementation run was the ExplorePostRoutePhysOpt. The 
above results are from the Post-Route report.

Utilization
+++++++++++

+-------------------+------+-------+--------------+-------+---------+
|Device             |FF(%) |LUT(%) |MEMORY LUT(%) |I/O(%) |DSP48(%) |
+===================+======+=======+==============+=======+=========+
|xc7kc325tffg900-2  |0.41  |0.43   |0.01          |7.8    |9.05     |
+-------------------+------+-------+--------------+-------+---------+
|xc7vx690tffg1761-2 |0.19  |0.20   |0.01          |4.59   |2.11     |
+-------------------+------+-------+--------------+-------+---------+
|xc7z020clg484-1    |1.58  |1.65   |0.01          |19.50  |34.55    |
+-------------------+------+-------+--------------+-------+---------+
|xc7a200tsbg484-2   |0.41  |0.43   |0.01          |7.8    |9.05     |
+-------------------+------+-------+--------------+-------+---------+



Max Clock Frequency
+++++++++++++++++++

+-------------------+----------------+
|Device             |Frequency (MHz) |
+===================+================+
|xc7kc325tffg900-2  |       322      |
+-------------------+----------------+
|xc7vx690tffg1761-2 |       320      |
+-------------------+----------------+
|xc7z020clg484-1    |       180      |
+-------------------+----------------+
|xc7a200tsbg484-2   |       221      |
+-------------------+----------------+